In a semiconductor memory device, for example, in a NAND flash memory, when a data write (data program) operation is executed, there is a case in which data program is executed separately in an even-BL (bit line) and an odd-BL (bit line). With the advancement of the generation, a parasitic capacitance has been increasing between neighboring BLs and between neighboring cells, leading to a greater interference effect between cells. In order to reduce the influence of an interference effect between neighboring cells in the BL direction, it is effective to divide neighboring bit lines BL0, BL1, BL2, . . . , into even-numbered BLs (even (BL)) and odd-numbered BLs (odd (BL)), and not to execute data program in the neighboring BLs at the same time (e.g. Jpn. Pat. Appln. KOKAI Publication No. 2002-279788).
According to this method, when data program is executed on the even (BL) side, the odd (BL) side is non-selected, and when data program is executed on the odd (BL) side, the even (BL) side is non-selected.